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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2006, zarlink semiconductor inc. all rights reserved. features ? meets jitter requirements of telcordia gr-253- core for oc-12, oc-3, and oc-1 rates ? meets jitter requirements of itu-t g.813 for stm- 4, and stm-1 rates ? provides one differential lvpecl output clock selectable to 19.44 mhz, 38.88 mhz, 77.76 mhz, 155.52 mhz, or 622.08 mhz ? provides a single-ended cmos output clock at 19.44 mhz ? accepts a single-ended cmos reference at 19.44 mhz or a differential lvds, lvpecl, or cml reference at 19.44 mhz or 77.76 mhz ? provides a lock indication ? 3.3 v supply applications ? sonet/sdh line cards description the zl30415 is an analog phase-locked loop (apll) designed to provide jitter attenuation and rate conversion for sdh (synchronous digital hierarchy) and sonet (synchronous optical network) networking equipment. the zl30415 generates low jitter output clocks that meet the jitter requirements of telcordia gr-253-core oc-12, oc-3, oc-1 rates and itu-t g.813 stm-4 and stm-1 rates. the zl30415 accepts a cmos compatible reference at 19.44 mhz or a differential lvds, lvpecl, or cml reference at 19.44 mhz or 77.76 mhz and generates a differential lvpecl output clock selectable to 19.44 mhz, 38.88 mhz, 77.76 mhz, 155.52 mhz, or 622.08 mhz, and a single-ended cmos clock at 19.44 mhz. the zl30415 provides a lock indication. september 2006 ordering information zl30415ggc 64 ball cabga trays zl30415ggf 64 ball cabga tape & reel, bake & drypack zl30415ggg2 64 ball cabga** trays, bake & drypack zl30415ggf2 64 ball cabga** tape & reel, bake & drypack **pb free tin/silver/copper -40 c to +85 c zl30415 sonet/sdh clock multiplier pll data sheet figure 1 - functional block diagram frequency detector vco frequency lpf oc-clkop/n vcc gnd vdd c19o fs2 loop filter bias & phase 19.44 mhz and 77.76 mhz state machine lock reference bias circuit and dividers and clock drivers c19o, c38o, c77o, c155o, c622o, lvpecl output c19i reference selection mux ref_sel ref_freq refinp/n c19oen c19i or c77i cml, lvds, lvpecl input 03 fs3 fs1
zl30415 data sheet 2 zarlink semiconductor inc. figure 2 - bga 64 ball package (top view) 1.0 ball description ball description table ball # name description a1, a2 a3 nc no internal bonding connection. leave unconnected. a4 a5 oc-clkop oc-clkon sonet/sdh clock (lvpecl output) . these outputs provide a selectable differential lvpecl clock at 19.44 h z, 38.88 mhz, 77.76 mhz, 155.52 mhz, and 622.08 mhz. the output frequency is selected with fs3, fs2 and fs1 inputs. a6 gnd ground. 0 volt a7, a8 b1, b2 nc no internal bonding connection. leave unconnected. b3 vcc1 positive analog power supply. +3.3 v +/-10% b4 gnd ground. 0 volt b5 nc no internal bonding connection. leave unconnected. b c d e f g h 12345678 1 1 - a1 corner is id entified by metallized markings. a lock vcc2 nc nc ref_freq nc nc nc vdd vdd gnd c19o vcc vdd ref_sel gnd gnd vcc vcc bias gnd gnd refinp fs1 fs2 gnd fs3 vcc gnd c19i gnd nc gnd gnd oc-clkop oc-clkon gnd gnd nc nc vcc1 nc nc gnd lpf gnd gnd gnd gnd nc refinn vdd vdd c19oen nc nc vdd vdd 8 mm x 8 mm ball pitch 0.8 mm nc nc nc nc gnd nc
zl30415 data sheet 3 zarlink semiconductor inc. b6, b7 gnd ground. 0 volt b8 vcc positive analog power supply. +3.3 v 10% c1 gnd ground. 0 volt c2 vcc2 positive analog power supply. +3.3 v 10% c3, c4 c5 gnd ground. 0 volt c6 nc no internal bonding connection. leave unconnected. c7 vdd positive digital power supply. +3.3 v 10% c8 gnd ground. 0 volt d1 bias bias circuit. d2 lpf external low-pass filter (analog). connect external rc network for the low- pass filter. d3 nc no internal bonding connection. leave unconnected. d4 gnd ground. 0 volt d5, d6 vcc positive analog power supply. +3.3 v 10% d7, d8 gnd ground. 0 volt e1 lock lock indicator (cmos output). this output goes high when the pll is frequency locked to the selected input reference. e2, e3 nc no internal bonding connection. leave unconnected. e4 g4 h5 fs2 fs3 fs1 frequency select 3-1 (cmos input) . these inputs select the clock frequency on the oc-clko output. the possible output frequencies are: 19.44 mhz (000), 38.88 mhz (001), 77. 76 mhz (010), 155.52 mhz (011), 622.08 (100) e5 vcc positive analog power supply. +3.3 v 10% e6 vdd positive digital power supply. +3.3 v 10% e7 nc no internal bonding connection. leave unconnected. e8 f8 refinn refinp differential reference clock input (cml/lvds/lvpecl compatible input) . these inputs accept a differential clock at 77.76 mhz or 19.44 mhz as the reference for synchronization. these inputs do not have on-chip ac coupling capacitors. f1, f2 nc no internal bonding connection. leave unconnected. f3 ref_freq reference frequency (cmos input) . this input selects the rate of the differential input clock (refinp/n) to be either 77.76 mhz or 19.44 mhz. f4 c19oen c19o output enable (cmos input). if tied high this control input enables the c19o output clock. pulling this pin lo w forces the output driver into a high impedance state. ball description table (continued) ball # name description
zl30415 data sheet 4 zarlink semiconductor inc. 2.0 functional description the zl30415 is an analog phased-locked loop which prov ides rate conversion and jitter attenuation for sonet/sdh oc-12/stm-4 and oc-3/stm-1 applications. a functional block diagram of the zl30415 is shown in figure 1 and a brief description is presented in the following sections. 2.1 reference se lection multiplexer the zl30415 accepts two types of input reference clocks: - differential: operating at 19.44 mhz or 77.76 mhz, compatible with lvds/lvpecl/cml threshold levels - single-ended: operating at 19.44 mhz, compatible with cmos switching levels. the ref_sel input determines whether the single-en ded cmos reference input (refin) or the differential reference inputs (refinp/n) are used as input reference clocks. the ref_freq input selects the rate of the differential input clock to be either 19.44 mhz, or 77.76 mhz. see table 1 for details. f5 c19i c19 reference input (cmos input). this is a single-ended input reference source used for synchronization. this input accepts 19.44 mhz. f6 c19o clock 19.44 mhz (cmos output) . this output provides a single-ended cmos clock at 19.44 mhz. f7, g1 gnd ground. 0 volt g2 vdd positive digital power supply. +3.3 v 10% g3 ref_sel reference select (cmos input). if tied low then the c19i single-ended reference is used as the input reference source. if tied high then the refinp/n differential pair is used as the input reference source. g4 fs3 see e4 ball description. g5, g6 gnd ground. 0 volt g7, g8 vdd positive digital power supply. +3.3 v 10% h1, h2 h3 nc no internal bonding connection. leave unconnected. h4 vdd positive digital power supply. +3.3 v 10% h5 fs1 see e4 ball description. h6 vdd positive digital power supply. +3.3 v 10% h7, h8 gnd ground. 0 volt. ref_sel ref_freq selected input reference reference frequency 0 x c19i 19.44 mhz (cmos) 1 0 refin 77.76 mhz (differential) 1 1 refin 19.44 mhz (differential) table 1 - input reference selection ball description table (continued) ball # name description
zl30415 data sheet 5 zarlink semiconductor inc. 2.2 frequency/phase detector the frequency/phase detector compares the frequency/p hase of the input referenc e signal with the feedback signal from the frequency divider circuit and prov ides an error signal equal to the frequency/phase difference between the two. this error signal is passed to the loop filter circuit. 2.3 lock indicator the zl30415 has a built-in lock detector that measures frequency difference between input reference clock c19i and the vco frequency. when the vco frequency is less than 300 ppm apart from the input reference frequency then the lock output is set high. the lock output is pulled low if the frequency difference exceeds 1000 ppm. 2.4 loop filter the loop filter is a low-pass filter. this low-pass filter eliminates high frequency spectral components from a phase error signal produced by the phase detector. this ensure s low output jitter that meets network jitter requirements. the corner frequency of the loo p filter is configurable with an external capacitor and resistor connected to the lpf ball and ground as shown in figure 3. figure 3 - loop filter elements 2.5 vco the voltage-controlled oscillator (vco) receives the fi ltered error signal from the loop filter, and based on the voltage of the error signal generates a primary frequency. the vco output is connected to the "frequency dividers and clock drivers" block that divides vco frequency and buffer generated clocks. r f c f zl30415 lpf r f =8.2 k ?, c f =470 nf filter loop frequency and phase detector vco
zl30415 data sheet 6 zarlink semiconductor inc. 2.6 frequency divi ders and clock drivers the output of the vco feeds the high frequency clock to the "frequency divi ders and clock drivers" circuit to provide one differential lvpecl comp atible clock with selectable frequency and one single-ended 19.44 mhz c19o output clock. the c19o clock can be enabled or dis abled with the associated c19oen output enable ball. internally, this block provides a feedback clock that closes the pll loop. the frequency of the oc-clko differential output clock is selected with fs3, fs2 and fs1 inputs as is shown in the following table. fs3 fs2 fs1 oc-clko frequency 0 0 0 19.44 mhz 0 0 1 38.88 mhz 0 1 0 77.76 mhz 0 1 1 155.52 mhz 1 0 0 622.08 mhz 101reserved 110reserved 111reserved table 2 - oc-clko clock frequency selection
zl30415 data sheet 7 zarlink semiconductor inc. 3.0 zl30415 performance the following are some of the zl30415 performance indicators that complement results lis ted in the characteristics section of this data sheet. 3.1 input jitter tolerance jitter tolerance is a measure of the pll?s ability to operat e properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter fr equencies) in the presence of jitter applied to its input reference. the input jitter tolerance of the zl30415 is show n in figure 4. on this graph, the single line at the top represents the input jitter tolerance and the three overl apping lines below represent the specification for minimum input jitter tolerance for oc-192, oc-48 and oc-12 netwo rk interfaces. the jitter tolerance is expressed in picoseconds (pk-pk) to accommodate requirements for interfaces operating at different rates. figure 4 - input jitter tolerance 3.2 jitter transfer characteristic jitter transfer characteristic represents a ratio of the jitter at the output of a p ll to the jitter applied to the input of a pll. this ratio is expressed in db and it characterizes t he pll?s ability to attenuate (filter) jitter. the zl30415 jitter transfer characteristic complies wi th the maximum 0.1 db jitter gain sp ecified in telcordia?s gr-253-core.
zl30415 data sheet 8 zarlink semiconductor inc. 4.0 applications 4.1 generation of low ji tter sonet/sdh equipment clocks the functionality and performance of the zl30415 complem ents the entire family of the zarlink?s advanced network synchronization pll?s. its jitter filtering characterist ics exceed requirements of sonet/sdh optical interfaces operating up to oc-12/stm-4 rates (622 mbit/s). the zl30415 in combination with the mt90401 or the zl30407 (sonet/sdh network element pll?s) provides the core bu ilding blocks for high quality equipment clocks suitable for network synchronization (see figure 5). figure 5 - sonet/sdh equipment clock zl30415 38.88 mhz 19.44 mhz oc-clkop/n lvpecl c19o cmos c19i c19o cmos c155o lvds c34o/c44o cmos c16o cmos c8o cmos c6o cmos 19.44 mhz c2o cmos c1.5o cmos f8o cmos f0o cmos 77.76 mhz 19.44 mhz 622.08 mhz 155.52 mhz c4o cmos 34.368 mhz or 44.736 mhz 16.384 mhz 8.192 mhz 6.312 mhz 4.096 mhz 2.048 mhz 1.544 mhz 8 khz 8 khz pri sec prior secor lock holdover refsel refalign r f lpf c f f s 1 155.52 mhz r e f _ s e l r e f _ f r e q f s 3 f s 2 c 1 9 o e n d s c s r / w a 0 - a 6 d 0 - d 7 up data port controller port synchronization reference clocks note: only main functional connections are shown. 20 mhz c 2 0 i f16o cmos ocxo 8 khz zl30407 l o c k refinp/n r f = 1 k ? c f = 470 nf
zl30415 data sheet 9 zarlink semiconductor inc. the zl30415 in combination with the mt9046 provides an optimum solution for sonet/sdh line cards (see figure 6). figure 6 - sonet/sdh line card mt9046 c19o cmos c16o cmos c8o cmos c6o cmos 19.44 mhz c2o cmos c1.5o cmos f8o cmos f0o cmos c4o cmos 16.384 mhz 8.192 mhz 6.312 mhz 4.096 mhz 2.048 mhz 1.544 mhz 8 khz 8 khz pri sec lock holdover rsel r 1 lpf c 1 m s 1 f s 2 f l o c k uc synchronization reference clocks note: only main functional connections are shown. 20 mhz f16o cmos tcxo 8 khz c 2 r 1 = 680 ? c 1 = 820 nf c 2 = 22 nf c20i m s 2 f s 1 p c c i hardware control t c l r zl30415 38.88 mhz 19.44 mhz oc-clkop/n lvpecl c19o cmos c19i 77.76 mhz 19.44 mhz 622.08 mhz f s 1 155.52 mhz r e f _ s e l r e f _ f r e q f s 3 f s 2 c 1 9 o e n l o c k refinp/n lpf
zl30415 data sheet 10 zarlink semiconductor inc. 4.2 recommended interface circuit 4.2.1 interfacing to refin receiver 4.2.1.1 interfacing refi n receiver to lvpecl driver the zl30415 refin differential receiver can be connected to lvpecl compatible driver with an interface circuit, as shown in figure 8. the r1s and r2s terminating resistors should be placed close to the refin input balls. figure 7 - interfacing to lvpecl driver 4.2.1.2 interfacing refin receiver to lvds or cml drivers the zl30415 refin differential receiver can be connected to lvds or cml driver with an interface circuit, as shown in figure 8. the 100 ? terminating resistors s hould be placed close to the refin input balls. figure 8 - interfacing to lvds or cml driver lvpecl z=50 ? z=50 ? typical resistor values: r1 = 127 ? , r2 = 82.5 ? r1 vcc=+3.3 v r1 driver zl30415 receiver cc vdd/2 cc refinp refinn r2 r2 zl30415 z=50 ? driver receiver z=50 ? cc vdd/2 lvds cc 100 ? refinp refinn or cml
zl30415 data sheet 11 zarlink semiconductor inc. 4.2.2 interfacing to oc-clko output 4.2.2.1 lvpecl to lvpecl interface the oc-clko outputs provide different ial lvpecl clocks at 622.08 mhz, 1 55.52 mhz, 77.76 mhz, 38.88 mhz and 19.44 mhz selectable with fs3, fs2 and fs1 frequency select inputs. the lvpecl output drivers require a 50 ? termination connected to the vcc-2v source for each output terminal at the terminating end as shown below. the terminating resistors should be placed close to the lvpecl receiver. figure 9 - lvpecl to lvpecl interface lvpecl lvpecl zl30415 z=50 ? z=50 ? oc-clkop oc-clkon receiver gnd typical resistor values: r1 = 127 ? , r2 =82.5 ? r1 r2 vcc=+3.3 v r1 r2 vcc 0.1uf +3.3 v driver
zl30415 data sheet 12 zarlink semiconductor inc. 4.3 power supply and bias circuit filtering recommendations figure 10 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. the level of required f iltering is subject to further optimi zation and simplification. please check zarlink?s web site for updates. figure 10 - power supply and bias circuit filtering notes: 1. all the ground pins (gnd) are connected to the same ground plane. 2. select ferrite bead with i dc > 400 ma and r dc in a range from 0.10 ? to 0.15 ?. b c d e f g h 12345678 1 a lock vcc2 nc nc ref_freq nc nc nc vdd vdd gnd c19o vcc vdd ref_sel gnd gnd vcc vcc bias gnd gnd refinp fs1 fs2 gnd fs3 vcc gnd c19i gnd nc gnd gnd oc-clkop oc-clkon gnd gnd nc nc vcc1 nc nc gnd lpf gnd gnd gnd gnd nc refinn vdd vdd c19oen nc nc vdd vdd nc nc nc nc gnd nc 0.1uf 10uf 0.1 uf ferrite bead 33uf 0.1uf 4.7 ? 220 ? 33uf 0.1uf 33uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf +3.3v power rail
zl30415 data sheet 13 zarlink semiconductor inc. 5.0 characteristics ? voltages are with respect to ground unless otherwise stated. ? exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? voltages are with respect to ground unless otherwise stated. ? typical figures are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings ? characteristics sym. min. ? max. ? units 1 supply voltage v ddr , v ccr tbd tbd v 2 voltage on any ball v ball -0.5 v cc + 0.5 v dd + 0.5 v 3 current on any ball i ball -0.5 30 ma 4 esd rating v esd 1250 v 5 storage temperature t st -55 125 c 6 package power dissipation p pd 1.0 w recommended operating conditions ? characteristics sym. min. typ. ? max. units notes 1 operating temperature t op -40 25 +85 c 2 positive supply v dd , v cc 3.0 3.3 3.6 v dc electrical characteristics ? characteristics sym. min. typ. ? max. units notes 1 supply current i dd +i cc 185 ma note 1 note 2 2 cmos: high-level input voltage v ih 0.7v dd v dd v 3 cmos: low-level input voltage v il 00.3v dd v 4 cmos: input leakage current i il 15uav i = v dd or 0v 5 cmos: input bias current for pulled-down inputs: fs1, fs2 and fs3 i b-pu 300 ua v i = v dd 6 cmos: input bias current for pulled-up inputs: c19oen i b-pd 90 ua v i = 0 v 7 cmos: high-level output voltage v oh 2.4 v i oh = 8 ma
zl30415 data sheet 14 zarlink semiconductor inc. ? voltages are with respect to ground unless otherwise stated. ? typical figures are for design aid only: not guaranteed and not subject to production testing. supply voltage and operating temperature are as per recommended operating conditions. note 1: the i lvpecl current is determined by th e external termination networ k connected to lvpecl outputs. more than 25% of this current (10 ma) flows outside the chip and it does not contribute to the internal power dissipation. the supply current value listed in the table includes this curren t to reflect total current cons umption of the zl30415 and the attached lvpecl termination network. note 2: lvpecl outputs terminated with z t = 50 ? resistors biased to v cc -2v (see figure 9). ? voltages are with respect to ground unless otherwise stated. figure 11 - output timing parameter measurement voltage levels 8 cmos: low-level output voltage v ol 0.4 v i ol = 4 ma 9 cmos: c19o output rise time t r 1.8 3.3 ns 18 pf load 10 cmos: c19o output fall time t f 1.1 1.4 ns 18 pf load 11 lvpecl: differential output voltage iv od_lvpecl i 1.30 v for 622 mhz note 2 12 lvpecl: offset voltage v os_lvpecl vcc- 1.38 vcc- 1.27 vcc- 1.15 v for 622 mhz note 2 13 lvpecl: output rise/fall times t rf 260 ps for 622 mhz note 2 ac electrical ch aracteristics ? - output timing parameters measurement voltage levels characteristics sym. cmos lvpecl units 1 threshold voltage v t-cmos v t-lvpecl 0.5v dd 0.5v od_lvpecl v 2 rise and fall threshold voltage high v hm 0.7v dd 0.8v od_lvpecl v 3 rise and fall threshold voltage low v lm 0.3v dd 0.2v od_lvpecl v dc electrical characteristics ? (continued) characteristics sym. min. typ. ? max. units notes v t all signals v hm v lm t if , t of t ir , t or timing reference points
zl30415 data sheet 15 zarlink semiconductor inc. ? supply voltage and operating temperature are as per recommended operating conditions. ? typical figures are for design aid only: not guaranteed and not subject to production testing. figure 12 - c19i input to c19o output timing ac electrical ch aracteristics ? - refin to c19o output timings figure 13 - refin input to c19o output timing ac electrical ch aracteristics ? - c19i input to c19o output timing characteristics sym. min. typ. ? max. units notes 1 c19i to c19o delay t c19d 4.4 6.7 9.4 ns characteristics sym. min. typ. ? max. units notes 1 refin (19.44 mhz) to c19o (19.44 mhz) delay t r19oc19d 1.4 7.8 10 ns 2 refin (77.76 mhz) to c19o (19.44 mhz) delay t r77oc77d 7.9 9.9 13 ns c19i v t-cmos (19.44 mhz) t c19d c19o v t-cmos (19.44 mhz) note: all output clocks have nominal 50% duty cycle. c19o v t-cmos v t-lvpecl t rw (77.76 mhz) refin v t-lvpecl (19.44 mhz) t r19oc19d t r77oc77d (19.44 mhz) refin
zl30415 data sheet 16 zarlink semiconductor inc. ac electrical ch aracteristics ? - c19i input to oc-clko output timing ? supply voltage and operating temperature are as per recommended operating conditions. ? typical figures are for design aid only: not guaranteed and not subject to production testing. figure 14 - c19i input to oc-clko output timing characteristics sym. min. typ. ? max. units notes 1 c19i(cmos) to c19o(lvpecl) delay t c19d 1.4 3.3 5.1 ns 2 c19i(cmos) to oc-clko(38) delay t c38d 1.2 3.0 4.8 ns 3 c19i(cmos) to oc-clko(77) delay t c77d 0.9 2.6 4.4 ns 4 c19i(cmos) to oc-clko(155) delay t c155d 0.6 2.3 4.1 ns 5 c19i(cmos) to oc-clko(622) delay t c622d 00.81.6ns 6 all output clock duty cycle d c 48 50 52 % oc-clko(38) v t-lvpecl c19i v t-cmos (19.44 mhz) t c19d oc-clko(19) v t-lvpecl (19.44 mhz) t c38d (38.88 mhz) oc-clko(155) v t-lvpecl (155.52 mhz) oc-clko(77) v t-lvpecl (77.76 mhz) t c77d t c155d note: all output clocks have nominal 50% duty cycle. oc-clko(622) v t-lvpecl (622.08 mhz) t c622d
zl30415 data sheet 17 zarlink semiconductor inc. ac electrical ch aracteristics ? - refin (19.44 mhz) input to oc-clko output timing ? supply voltage and operating temperature are as per recommended operating conditions. ? typical figures are for design aid only: not guaranteed and not subject to production testing. figure 15 - refin (19.44 mhz) input to oc-clko output timing characteristics sym. min. typ. ? max. units notes 1 refin(19.44 mhz) to oc-clko(19) delay t c19-19d 2.4 4.3 6.2 ns 2 refin(19.44 mhz) to oc-clko(38) delay t c19-38d 1.9 4.0 6.0 ns 3 refin(19.44 mhz) to oc-clko(77) delay t c19-77d 1.7 3.7 5.6 ns 4 refin(19.44 mhz) to oc-clko(155) delay t c19-155d 1.4 3.4 5.3 ns 5 refin(19.44 mhz) to oc-clko(622) delay t c19-622d 00.81.6ns oc-clko(38) refin v t-lvpecl (19.44 mhz) t c19-19d oc-clko(19) v t-lvpecl (19.44 mhz) (38.88 mhz) oc-clko(155) (155.52 mhz) oc-clko(77) (77.76 mhz) note: all output clocks have nominal 50% duty cycle. oc-clko(622) (622.08 mhz) v t-lvpecl t c19-38d v t-lvpecl v t-lvpecl t c19-77d t c19-155d v t-lvpecl t c19-622d
zl30415 data sheet 18 zarlink semiconductor inc. ac electrical ch aracteristics ? - refin (77.76 mhz) input to oc-clko output timing ? supply voltage and operating temperature are as per recommended operating conditions. ? typical figures are for design aid only: not guaranteed and not subject to production testing. figure 16 - refin (77.76 mhz) input to oc-clko output timing characteristics sym. min. typ. ? max. units notes 1 refin(77.76 mhz) to oc-clko(19) delay t c77-19d 3.5 6.5 9.5 ns 2 refin(77.76 mhz) to oc-clko(38) delay t c77-38d 3.2 6.2 9.2 ns 3 refin(77.76 mhz) to oc-clko(77) delay t c77-77d 2.9 5.9 8.8 ns 4 refin(77.76 mhz) to oc-clko(155) delay t c77-155d 2.6 5.6 8.6 ns 5 refin(77.76 mhz) to oc-clko(622) delay t c77-622d 00.81.6ns oc-clko(38) v t-lvpecl refin v t-lvpecl (77.76 mhz) t c77-19d oc-clko(19) v t-lvpecl (19.44 mhz) t c77-38d (38.88 mhz) oc-clko(155) v t-lvpecl (155.52 mhz) oc-clko(77) v t-lvpecl (77.76 mhz) t c77-77d t c77-155d note: all output clocks have nominal 50% duty cycle. oc-clko(622) v t-lvpecl (622.08 mhz) t c77-622d
zl30415 data sheet 19 zarlink semiconductor inc. ? typical figures are for design aid only: not guaranteed and not subject to production testing. ? loop filter components: r f = 8.2 k ?, c f = 470 nf. performance characteristics - functional (vcc = 3.3 v 10%; ta = -40 to 85c ) characteristics min. typ. max. units notes 1 pull-in range 1000 ppm at nominal input reference frequency c19i = 19.44 mhz 2 lock time 300 ms performance characteristics: outp ut jitter generation (lvpecl: 19.44 mhz, 38.88 mhz, 77.76 mhz, 155.52 mhz, and 622.08 mhz and cmos: 19.44 mhz) - gr-253-core conformance - (v cc = 3.3 v 10%; t a = - 40 to 85 c) gr-253-core jitter generation requirements zl30415 jitter generation performance interface (category ii) jitter measurement filter limit in ui equivalent limit in time domain typ. ? max. ? units 1oc-12 sts-12 12 khz - 5 mhz 0.1 uipp 161 35 ps p-p 0.01 ui rms 16.1 1.7 3.5 ps rms 2oc-3 sts-3 12 khz - 1.3 mhz 0.1 uipp 643 33 ps p-p 0.01 ui rms 64.3 1.6 3.3 ps rms
zl30415 data sheet 20 zarlink semiconductor inc. ? typical figures are for design aid only: not guaranteed and not subject to production testing. ? loop filter components: r f = 8.2 k ?, c f = 470 nf. performance characteristics: outp ut jitter generation (lvpecl: 19.44 mhz, 38.88 mhz, 77.76 mhz, 155.52 mhz, and 622.08 mhz and cmos: 19.44 mhz) - etsi en 300 462-7-1 conformance - (v cc = 3.3 v 10%; t a = -40 to 85 c) en 300 462-7-1 jitter generation requir ements zl30415 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ. ? max. ? units 1stm-4 250 khz to 5 mhz 0.1 uipp 161 30 ps p-p --1.53ps rms 1 khz to 5 mhz 0.5 uipp 804 80 ps p-p --48ps rms 2stm-1 optical 65 khz to 1.3 mhz 0.1 uipp 643 31 ps p-p --1.63.1ps rms 500 hz to 1.3 mhz 0.5 uipp 3215 100 ps p-p --510ps rms 3stm-1 electrical 65 khz to 1.3 mhz 0.075 uipp 482 31 ps p-p --1.63.1ps rms 500 hz to 1.3 mhz 0.5 uipp 3215 100 ps p-p --510ps rms
zl30415 data sheet 21 zarlink semiconductor inc. ? typical figures are for design aid only: not guaranteed and not subject to production testing. ? loop filter components: r f = 8.2 k ?, c f = 470 nf. performance characteristics: outp ut jitter generation (lvpecl: 19.44 mhz, 38.88 mhz, 77.76 mhz, 155.52 mhz, and 622.08 mhz and cmos: 19.44 m hz) - g.813 conformance (option 1 and 2) - (v cc = 3.3 v 10%; t a = -40 to 85 c) g.813 jitter generation requirements zl30415 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ. ? max. ? units option 1 1 stm-4 250 khz to 5 mhz 0.1 uipp 161 30 ps p-p --1.53ps rms 1 khz to 5 mhz 0.5 uipp 804 80 ps p-p --48ps rms 2 stm-1 65 khz to 1.3 mhz 0.1 uipp 643 31 ps p-p --1.63.1ps rms 500 hz to 1.3 mhz 0.5 uipp 3215 100 ps p-p --510ps rms option 2 3 stm-4 12 khz - 5 mhz 0.1 uipp 161 35 ps p-p --1.73.5ps rms 4 stm-1 12 khz - 1.3 mhz 0.1 uipp 643 33 ps p-p --1.63.3ps rms
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